Lab 2 – Converting Fixed-Point to
Floating-Point and Vice Versa
Prelab
You will need to write your own testbench and submit it on ilearn prior to coming to the lab
(check online for due dates). Your testbench should demonstrate that you have read through
the lab specifications and understand the goal of this lab. You will need to consider the
boundary cases. You do not need to begin designing yet, but this testbench will be helpful
during the lab while you are designing.
Introduction
This lab consists of 2 parts. In the first part, you will develop a Verilog simulation to convert a
fixed-point binary number to a single-precision floating-point number. In the second part, you
will extend your program to support the opposite i.e. from floating point to fixed point.
● A floating-point tutorial can be found here.
● Your code MUST handle 0 input and negative inputs.
Part 1 – Fixed-Point to Floating-Point
You will receive two inputs representing the fixed point value. The first value will be the number
of bits to the right of the binary point. The second value will be a 32-bit fixed-point number (read
as a 2’s complement integer). You can assume the values given will not be out of range. You
will create a module using the template provided (fixedToFloat.v) in the zip file and
implement the fixed to floating-point operation. Your Verilog simulation should output the
floating-point number.
Fixed-Point as an Integer:
Assume we want to represent 8.25 as an integer in 32.7 format (7 bits to the right of the binary
point).
● 8.25 in binary is 1000 . 01
● Extend to 7 bits to the right of the binary point
1000 . 010 0000
● Extending to 32 total bits, maintaining the binary point:
0000 0000 0000 0000 0000 0100 0 . 010 0000
○ To hex: 0xh0000 0420
○ To an integer: 1056 (Ignoring the radix point)
https://docs.google.com/document/d/1v7Yy7_2WZaCXQR-bDAsG1uVYpj221GcjCkuRH2lH18o/edit?usp=sharing
Fixed-Point to Single-Precision Floating-Point Conversion
Input : 7 , 1056 ( i.e. 0xh07, 0xh00000420 )
Output : 8.25 as single-precision FFP ( i.e 0_10000010_0000_1000_0000_0000_0000_000 or
0x41040000 )
Part 2 – Floating-Point to Fixed-Point
You will receive two inputs, the first value will be the desired number of bits to the right of the
binary point on the output. The second value will be a 32-bit floating-point number. You can
assume the values given will not be out of range. You will create a module using the template
proved (floatToFixed.v) in the zip file and implement the floating-point to fixed-point
operation. Your Verilog simulation should output the fixed-point number.
Sample Input:
7 ( i.e 0xh07)
8.25 as single precision FFP
( i.e 0_10000010_0000_1000_0000_0000_0000_000 = 0xh41040000 )
Sample Output:
1056 ( i.e 0xh00000420 )
Mandatory functionality
● User inputs will be specified in the testbench
● Floating-point outputs must be formatted as floating-point values
● Fixed point outputs can be formatted as integer values
Part 3
You will now create the top-level module for this project using the template provided
(fixedFloatConversion.v). This top-level module should support both fixed to float and
float to fixed-point conversion. Which module you use is configured by the opcode input (1 for
floatToFixed and 0 for fixedToFloat).
Submission:
Each student must turn in one zip file to Gradescope. The contents of which should be:
● A README file with your name and email address, and any incomplete or incorrect
functionality
● All Verilog file(s) used in this lab (implementation and test benches).
If your file does not synthesize or simulate properly, you will receive a 0 on the lab.
fixedFloatConversion
#! /usr/bin/vvp
:ivl_version “10.3 (stable)”;
:ivl_delay_selection “TYPICAL”;
:vpi_time_precision – 12;
:vpi_module “system”;
:vpi_module “vhdl_sys”;
:vpi_module “v2005_math”;
:vpi_module “va_math”;
S_0x55ededa78fc0 .scope module, “fixedFloatConversion_tb” “fixedFloatConversion_tb” 2 18;
.timescale -9 -12;
v0x55ededaa86d0_0 .var “R”, 31 0;
v0x55ededaa87d0_0 .var “clk”, 0 0;
v0x55ededaa8890_0 .var/i “failedTests”, 31 0;
v0x55ededaa8930_0 .var “fixpointpos”, 4 0;
v0x55ededaa89f0_0 .var “opcode”, 0 0;
v0x55ededaa8ae0_0 .net “resultnumber”, 31 0, v0x55ededaa8330_0; 1 drivers
v0x55ededaa8b80_0 .var “rst”, 0 0;
v0x55ededaa8c20_0 .var “targetnumber”, 31 0;
v0x55ededaa8cc0_0 .var/i “totalTests”, 31 0;
E_0x55ededa80b40 .event negedge, v0x55ededaa7610_0;
S_0x55ededa77a00 .scope module, “uut” “fixedFloatConversion” 2 32, 3 22 0, S_0x55ededa78fc0;
.timescale -9 -12;
.port_info 0 /INPUT 1 “clk”
.port_info 1 /INPUT 1 “rst”
.port_info 2 /INPUT 32 “targetnumber”
.port_info 3 /INPUT 5 “fixpointpos”
.port_info 4 /INPUT 1 “opcode”
.port_info 5 /OUTPUT 32 “result”
v0x55ededaa7ee0_0 .net “clk”, 0 0, v0x55ededaa87d0_0; 1 drivers
v0x55ededaa7ff0_0 .net “fixpointpos”, 4 0, v0x55ededaa8930_0; 1 drivers
v0x55ededaa8100_0 .net “fixresult”, 31 0, v0x55ededaa7ca0_0; 1 drivers
v0x55ededaa81a0_0 .net “floatresult”, 31 0, v0x55ededaa7550_0; 1 drivers
v0x55ededaa8240_0 .net “opcode”, 0 0, v0x55ededaa89f0_0; 1 drivers
v0x55ededaa8330_0 .var “result”, 31 0;
v0x55ededaa8410_0 .net “rst”, 0 0, v0x55ededaa8b80_0; 1 drivers
v0x55ededaa8500_0 .net “targetnumber”, 31 0, v0x55ededaa8c20_0; 1 drivers
E_0x55ededa4b8b0 .event posedge, v0x55ededa4a860_0;
S_0x55ededa829d0 .scope module, “fixToFloat” “fixedToFloat” 3 36, 4 18 0, S_0x55ededa77a00;
.timescale -9 -12;
.port_info 0 /INPUT 1 “clk”
.port_info 1 /INPUT 1 “rst”
.port_info 2 /INPUT 32 “targetnumber”
.port_info 3 /INPUT 5 “fixpointpos”
.port_info 4 /OUTPUT 32 “result”
v0x55ededa4a860_0 .net “clk”, 0 0, v0x55ededaa87d0_0; alias, 1 drivers
v0x55ededaa7470_0 .net “fixpointpos”, 4 0, v0x55ededaa8930_0; alias, 1 drivers
v0x55ededaa7550_0 .var “result”, 31 0;
v0x55ededaa7610_0 .net “rst”, 0 0, v0x55ededaa8b80_0; alias, 1 drivers
v0x55ededaa76d0_0 .net “targetnumber”, 31 0, v0x55ededaa8c20_0; alias, 1 drivers
E_0x55ededa80520 .event edge, v0x55ededaa76d0_0;
S_0x55ededaa78a0 .scope module, “floatToFix” “floatToFixed” 3 43, 5 18 0, S_0x55ededa77a00;
.timescale -9 -12;
.port_info 0 /INPUT 1 “clk”
.port_info 1 /INPUT 1 “rst”
.port_info 2 /INPUT 32 “float”
.port_info 3 /INPUT 5 “fixpointpos”
.port_info 4 /OUTPUT 32 “result”
v0x55ededaa7a90_0 .net “clk”, 0 0, v0x55ededaa87d0_0; alias, 1 drivers
v0x55ededaa7b30_0 .net “fixpointpos”, 4 0, v0x55ededaa8930_0; alias, 1 drivers
v0x55ededaa7bd0_0 .net “float”, 31 0, v0x55ededaa8c20_0; alias, 1 drivers
v0x55ededaa7ca0_0 .var “result”, 31 0;
v0x55ededaa7d40_0 .net “rst”, 0 0, v0x55ededaa8b80_0; alias, 1 drivers
.scope S_0x55ededa829d0;
T_0 ;
%wait E_0x55ededa80520;
%load/vec4 v0x55ededaa76d0_0;
%store/vec4 v0x55ededaa7550_0, 0, 32;
%jmp T_0;
.thread T_0, $push;
.scope S_0x55ededaa78a0;
T_1 ;
%wait E_0x55ededa80520;
%load/vec4 v0x55ededaa7bd0_0;
%store/vec4 v0x55ededaa7ca0_0, 0, 32;
%jmp T_1;
.thread T_1, $push;
.scope S_0x55ededa77a00;
T_2 ;
%wait E_0x55ededa4b8b0;
%load/vec4 v0x55ededaa8240_0;
%pad/u 32;
%cmpi/e 1, 0, 32;
%flag_mov 8, 4;
%jmp/0 T_2.0, 8;
%load/vec4 v0x55ededaa8100_0;
%jmp/1 T_2.1, 8;
T_2.0 ; End of true expr.
%load/vec4 v0x55ededaa81a0_0;
%jmp/0 T_2.1, 8;
; End of false expr.
%blend;
T_2.1;
%assign/vec4 v0x55ededaa8330_0, 0;
%jmp T_2;
.thread T_2;
.scope S_0x55ededa78fc0;
T_3 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55ededaa8890_0, 0, 32;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55ededaa8cc0_0, 0, 32;
%end;
.thread T_3;
.scope S_0x55ededa78fc0;
T_4 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55ededaa87d0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55ededaa8b80_0, 0, 1;
%delay 50000, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55ededaa87d0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55ededaa8b80_0, 0, 1;
%delay 50000, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55ededaa87d0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55ededaa8b80_0, 0, 1;
%delay 50000, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55ededaa87d0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55ededaa8b80_0, 0, 1;
%delay 50000, 0;
T_4.0 ;
%load/vec4 v0x55ededaa87d0_0;
%inv;
%store/vec4 v0x55ededaa87d0_0, 0, 1;
%delay 50000, 0;
%jmp T_4.0;
%end;
.thread T_4;
.scope S_0x55ededa78fc0;
T_5 ;
%wait E_0x55ededa80b40;
%wait E_0x55ededa4b8b0;
%delay 10000, 0;
%pushi/vec4 0, 0, 5;
%store/vec4 v0x55ededaa8930_0, 0, 5;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55ededaa8c20_0, 0, 32;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55ededaa86d0_0, 0, 32;
%vpi_call 2 65 “$display”, “Test Group 1: Testing Floating point to fixed point… ” {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55ededaa89f0_0, 0, 1;
%vpi_call 2 68 “$write”, “\011Test Case 1.1: Convert 25.25 (011001.01,2=>0 10000011 1001010..)…” {0 0 0};
%load/vec4 v0x55ededaa8cc0_0;
%addi 1, 0, 32;
%store/vec4 v0x55ededaa8cc0_0, 0, 32;
%pushi/vec4 2, 0, 5;
%store/vec4 v0x55ededaa8930_0, 0, 5;
%pushi/vec4 101, 0, 32;
%store/vec4 v0x55ededaa8c20_0, 0, 32;
%pushi/vec4 1103757312, 0, 32;
%store/vec4 v0x55ededaa86d0_0, 0, 32;
%delay 100000, 0;
%load/vec4 v0x55ededaa86d0_0;
%load/vec4 v0x55ededaa8ae0_0;
%cmp/ne;
%jmp/0xz T_5.0, 4;
%vpi_call 2 76 “$display”, “failed: Expected: %b, got %b”, v0x55ededaa86d0_0, v0x55ededaa8ae0_0 {0 0 0};
%load/vec4 v0x55ededaa8890_0;
%addi 1, 0, 32;
%store/vec4 v0x55ededaa8890_0, 0, 32;
%jmp T_5.1;
T_5.0 ;
%vpi_call 2 79 “$display”, “passed” {0 0 0};
T_5.1 ;
%vpi_call 2 89 “$display”, “Test Group 2: Testing Fixed point to floating point… ” {0 0 0};
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55ededaa89f0_0, 0, 1;
%vpi_call 2 92 “$write”, “\011Test Case 2.1: 25.25 (0 10000011 1001010,2=>011001.01)…” {0 0 0};
%load/vec4 v0x55ededaa8cc0_0;
%addi 1, 0, 32;
%store/vec4 v0x55ededaa8cc0_0, 0, 32;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55ededaa89f0_0, 0, 1;
%pushi/vec4 2, 0, 5;
%store/vec4 v0x55ededaa8930_0, 0, 5;
%pushi/vec4 1103757312, 0, 32;
%store/vec4 v0x55ededaa8c20_0, 0, 32;
%pushi/vec4 101, 0, 32;
%store/vec4 v0x55ededaa86d0_0, 0, 32;
%delay 100000, 0;
%load/vec4 v0x55ededaa86d0_0;
%load/vec4 v0x55ededaa8ae0_0;
%cmp/ne;
%flag_mov 8, 4;
%load/vec4 v0x55ededaa8ae0_0;
%cmpi/e 0, 4294967295, 32;
%flag_or 6, 8;
%jmp/0xz T_5.2, 6;
%vpi_call 2 100 “$display”, “failed: Expected: %b, got %b”, v0x55ededaa86d0_0, v0x55ededaa8ae0_0 {0 0 0};
%load/vec4 v0x55ededaa8890_0;
%addi 1, 0, 32;
%store/vec4 v0x55ededaa8890_0, 0, 32;
%jmp T_5.3;
T_5.2 ;
%vpi_call 2 103 “$display”, “passed” {0 0 0};
T_5.3 ;
%vpi_call 2 113 “$write”, “\012————————————————————–” {0 0 0};
%load/vec4 v0x55ededaa8cc0_0;
%load/vec4 v0x55ededaa8890_0;
%sub;
%vpi_call 2 114 “$write”, “\012Testing complete\012Passed %0d / %0d tests”, S<0,vec4,s32>, v0x55ededaa8cc0_0 {1 0 0};
%vpi_call 2 115 “$write”, “\012————————————————————–\012” {0 0 0};
%vpi_call 2 116 “$finish” {0 0 0};
%end;
.thread T_5;
# The file index is used to find the file name in the following table.
:file_names 6;
“N/A”;
“
“fixedFloatConversion_tb.v”;
“fixedFloatConversion.v”;
“fixedToFloat.v”;
“floatToFixed.v”;
fixedFloatConversion.v
//=========================================================================
// Name & Email must be EXACTLY as in Gradescope roster!
// Name:
// Email:
//
// Assignment name:
// Lab section:
// TA:
//
// I hereby certify that I have not received assistance on this assignment,
// or used code, from ANY outside source other than the instruction team
// (apart from what was provided in the starter file).
//
//=========================================================================
// ————————————————————————
// This file does not need any changes, other than your information above
// ————————————————————————
`timescale 1ns / 1ps
module fixedFloatConversion(
input wire clk,
input wire rst ,
input wire[31:0] targetnumber,
input wire[4:0] fixpointpos ,
input wire opcode , // 1 is float to fix, 0 is fix to float
output reg[31:0] result );
wire [31:0] floatresult ;
wire [31:0] fixresult ;
// ——————————————-
// From fix to float (Part 1)
// ——————————————-
fixedToFloat fixToFloat(.clk(clk),.rst(rst),
.targetnumber(targetnumber),.fixpointpos(fixpointpos),
.result(floatresult));
// ——————————————-
// From float to fix (Part 2)
// ——————————————-
floatToFixed floatToFix(.clk(clk),.rst(rst),
.float(targetnumber),.fixpointpos(fixpointpos),
.result(fixresult));
// ——————————————-
// Register the results
// ——————————————-
always @ ( posedge clk ) begin
// Implement your synchronous reset
result <= opcode == 1 ? fixresult : floatresult ;
end
endmodule
fixedFloatConversion_tb.v
//=========================================================================
// Name & Email must be EXACTLY as in Gradescope roster!
// Name:
// Email:
//
// Assignment name:
// Lab section:
// TA:
//
// I hereby certify that I have not received assistance on this assignment,
// or used code, from ANY outside source other than the instruction team
// (apart from what was provided in the starter file).
//
//=========================================================================
`timescale 1ns / 1ps
module fixedFloatConversion_tb;
// Inputs
reg clk;
reg rst;
reg [31:0] targetnumber;
reg [4:0] fixpointpos;
reg opcode;
wire [31:0] resultnumber;
reg [31:0] R;
// ---------------------------------------------------
// Instantiate the Unit Under Test (UUT)
// ---------------------------------------------------
fixedFloatConversion uut (
.clk( clk ) ,
.rst(rst) ,
.targetnumber(targetnumber),
.fixpointpos(fixpointpos),
.opcode(opcode) ,
.result(resultnumber)
);
initial begin
clk = 0; rst = 1; #50;
clk = 1; rst = 1; #50;
clk = 0; rst = 0; #50;
clk = 1; rst = 0; #50;
forever begin
clk = ~clk; #50;
end
end
integer failedTests = 0;
integer totalTests = 0;
initial begin
// Reset
@(negedge rst); // Wait for reset to be released (from another initial block)
@(posedge clk); // Wait for first clock out of reset
#10; // Wait
fixpointpos = 4'b0000;
targetnumber = { 32'h0 };
R = { 32'h0 };
// -------------------------------------------------------
// Test group 1: Floating point to fixed point
// -------------------------------------------------------
$display("Test Group 1: Testing Floating point to fixed point... ");
opcode = 1'b0;
$write("\tTest Case 1.1: Convert 25.25 (011001.01,2=>0 10000011 1001010..)…”);
totalTests = totalTests + 1;
// Set inputs
fixpointpos = 4’b0010;
targetnumber = { {24’h000000}, {8’b011001_01} };
R = 32’b0_10000011_10010100000000000000000;
#100; // Wait
if (R != resultnumber) begin
$display(“failed: Expected: %b, got %b”, R, resultnumber);
failedTests = failedTests + 1;
end else begin
$display(“passed”);
end
// ——————————————————-
// Put your tests here
// ——————————————————-
// ——————————————————-
// Test group 2: Fixed point to floating point
// ——————————————————-
$display(“Test Group 2: Testing Fixed point to floating point… “);
opcode = 1’b1;
$write(“\tTest Case 2.1: 25.25 (0 10000011 1001010,2=>011001.01)…”);
totalTests = totalTests + 1;
opcode = 1’b1;
fixpointpos = 4’b0010;
targetnumber = 32’b0_10000011_10010100000000000000000;
R = { {24’h000000}, {8’b011001_01} };
#100;
if ( R != resultnumber || resultnumber === 32’bz) begin
$display(“failed: Expected: %b, got %b”, R, resultnumber);
failedTests = failedTests + 1;
end else begin
$display(“passed”);
end
// ——————————————————-
// Put your tests here
// ——————————————————-
// ————————————————————–
// End testing
// ————————————————————–
$write(“\n————————————————————–“);
$write(“\nTesting complete\nPassed %0d / %0d tests”,totalTests-failedTests,totalTests);
$write(“\n————————————————————–\n”);
$finish();
end
endmodule
fixedToFloat.v
//=========================================================================
// Name & Email must be EXACTLY as in Gradescope roster!
// Name:
// Email:
//
// Assignment name:
// Lab section:
// TA:
//
// I hereby certify that I have not received assistance on this assignment,
// or used code, from ANY outside source other than the instruction team
// (apart from what was provided in the starter file).
//
//=========================================================================
`timescale 1ns / 1ps
module fixedToFloat(
input wire clk,
input wire rst ,
input wire[31:0] targetnumber,
input wire[4:0] fixpointpos ,
output reg[31:0] result );
// Your Implementation
// ——————————————-
// Register the results
// ——————————————-
always @(*) begin
// Replace the following code with your implmentation
result = targetnumber;
end
endmodule
Floating Point Tutorial
Floating Point Tutorial
In single precision floating point you have:
● A sign (+ or -), represented by 1 bit
● The exponent, represented by 8 bits
● The fraction, represented by 23 bits
So altogether you represent a single precision floating point number in 32 bits.
Example: 25.75 (from slides)
1. Convert number into “hybrid” binary.
Convert 25 into binary → 11001
Convert .75 into binary… here’s a little trick:
So now, 0.75 in binary is 11. You can fill in zeros after the “11”, so it can be “110” or
“11000”.
The complete hybrid binary is: 11001.110
2. Float the binary point.
You need to normalize the mantissa to 1.1001110. Shift the radix point to have only one
1 to the left of the radix.
Ex 1: 1110.0001 → 1.1100001 Ex 2: 00.111001001 → 1.11001001
To make the number 1.1001110, you had to move the radix point 4 places to the left.
1 bit 8 bits 23 bits
sign Biased exponent fraction
Trick Bits
1. Take the decimal (.75) and
multiply by 2
0.75
x 2
2. If you get a 1, this bit is a 1. If you
get a 0, this bit is a 0
1.50
1
3. Take the decimal part of 1.50
(which is 0.50) and multiply by 2
0.50
x 2
4. When you have all 0’s for the
decimal part, you’re done
1.00
1
When you do so, you need to keep track of how many places you moved it, this is
represented in an exponent: 24. Remember, this is in binary so the base is 2 NOT 10.
Now, our value is 1.1001110 x 24
3. Floating point representation:
Now you need to fill in the fields.
a. Sign: the number initially was positive, so we represent the sign as 0
b. Exponent: the value is 4, but the rule of filling in this field is to add 127 to the
initial exponent value to create the biased exponent. 4 + 127 = 131
c. Fraction: the numbers right of the radix point is the fraction. In the value
1.1001110, we care about the 1001110. We then extend the value (add 0’s to the
right) to 23 bits.
Our final representation is 0 1000 0011 1001 1100 0000 0000 0000 000
sign exponent fraction
0
sign exponent fraction
0 1000 0011
sign exponent fraction
0 1000 0011 1001 1100 0000 0000 0000 000
Example: 1.125
“Hybrid” binary → 1.001
Example: 2.625
“Hybrid” binary → 10.101
Trick Bits
0.125
x
2
Whole number is a 0, so bit is a 0 0.250
0
0.250
x 2
Whole number is a 0, so bit is a 0 0.500
0
0.500
x 2
Whole number is a 1, so bit is a 1
Decimal is a 0, so done.
1.000
1
Trick Bits
0.625
x 2
Whole number is a 1, so bit is a 1 1.250
1
0.250
x 2
Whole number is a 0, so bit is a 0 0.500
0
0.500
x 2
Whole number is a 1, so bit is a 1
Decimal is a 0, so done.
1.000
1
floatToFixed.v
//=========================================================================
// Name & Email must be EXACTLY as in Gradescope roster!
// Name:
// Email:
//
// Assignment name:
// Lab section:
// TA:
//
// I hereby certify that I have not received assistance on this assignment,
// or used code, from ANY outside source other than the instruction team
// (apart from what was provided in the starter file).
//
//=========================================================================
`timescale 1ns / 1ps
module floatToFixed(
input wire clk,
input wire rst ,
input wire[31:0] float,
input wire[4:0] fixpointpos ,
output reg[31:0] result );
// Your Implementation
// ——————————————-
// Register the results
// ——————————————-
always @(*) begin
// Replace the following code with your implmentation
result = float;
end
endmodule
Lab 02 – Fixed Point
Lab 2 – Converting Fixed-Point to
Floating-Point and Vice Versa
Prelab
You will need to write your own testbench and submit it on ilearn prior to coming to the lab
(check online for due dates). Your testbench should demonstrate that you have read through
the lab specifications and understand the goal of this lab. You will need to consider the
boundary cases. You do not need to begin designing yet, but this testbench will be helpful
during the lab while you are designing.
Introduction
This lab consists of 2 parts. In the first part, you will develop a Verilog simulation to convert a
fixed-point binary number to a single-precision floating-point number. In the second part, you
will extend your program to support the opposite i.e. from floating point to fixed point.
● A floating-point tutorial can be found here.
● Your code MUST handle 0 input and negative inputs.
Part 1 – Fixed-Point to Floating-Point
You will receive two inputs representing the fixed point value. The first value will be the number
of bits to the right of the binary point. The second value will be a 32-bit fixed-point number (read
as a 2’s complement integer). You can assume the values given will not be out of range. You
will create a module using the template provided (fixedToFloat.v) in the zip file and
implement the fixed to floating-point operation. Your Verilog simulation should output the
floating-point number.
Fixed-Point as an Integer:
Assume we want to represent 8.25 as an integer in 32.7 format (7 bits to the right of the binary
point).
● 8.25 in binary is 1000 . 01
● Extend to 7 bits to the right of the binary point
1000 . 010 0000
● Extending to 32 total bits, maintaining the binary point:
0000 0000 0000 0000 0000 0100 0 . 010 0000
○ To hex: 0xh0000 0420
○ To an integer: 1056 (Ignoring the radix point)
https://docs.google.com/document/d/1v7Yy7_2WZaCXQR-bDAsG1uVYpj221GcjCkuRH2lH18o/edit?usp=sharing
Fixed-Point to Single-Precision Floating-Point Conversion
Input : 7 , 1056 ( i.e. 0xh07, 0xh00000420 )
Output : 8.25 as single-precision FFP ( i.e 0_10000010_0000_1000_0000_0000_0000_000 or
0x41040000 )
Part 2 – Floating-Point to Fixed-Point
You will receive two inputs, the first value will be the desired number of bits to the right of the
binary point on the output. The second value will be a 32-bit floating-point number. You can
assume the values given will not be out of range. You will create a module using the template
proved (floatToFixed.v) in the zip file and implement the floating-point to fixed-point
operation. Your Verilog simulation should output the fixed-point number.
Sample Input:
7 ( i.e 0xh07)
8.25 as single precision FFP
( i.e 0_10000010_0000_1000_0000_0000_0000_000 = 0xh41040000 )
Sample Output:
1056 ( i.e 0xh00000420 )
Mandatory functionality
● User inputs will be specified in the testbench
● Floating-point outputs must be formatted as floating-point values
● Fixed point outputs can be formatted as integer values
Part 3
You will now create the top-level module for this project using the template provided
(fixedFloatConversion.v). This top-level module should support both fixed to float and
float to fixed-point conversion. Which module you use is configured by the opcode input (1 for
floatToFixed and 0 for fixedToFloat).
Submission:
Each student must turn in one zip file to Gradescope. The contents of which should be:
● A README file with your name and email address, and any incomplete or incorrect
functionality
● All Verilog file(s) used in this lab (implementation and test benches).
If your file does not synthesize or simulate properly, you will receive a 0 on the lab.
