Handwork
1.1 – D Flip Flop
Add Truth
Table Here
Add Timing Diagram Here
1.2 – T Flip Flop
Add Truth
Table Here
Add Timing Diagram Here
1.3 – S-R Flip Flop
Add Truth
Table Here
Add Timing Diagram Here
1.4 – J-K Flip Flop
Add Truth
Table Here
Add Timing Diagram Here
1.5 – Excita@on Tables
Add
Excita*on
Table Here
Add
Excita*on
Table Here
Add
Excita*on
Table Here
2 – Design and Simula@on of Sequen@al Components in Altera Quartus using VHDL
2.1 – Data Flip Flop (DFF)
Add your
Project Wizard
Se2ngs snip
HERE
Add your VHDL
Code Here
Add
Excita*on
Table Here
Add Successful
Compila7on Snip
Here
Add Timing Diagram
Here
2.2 – 1-Bit Register
Add your
Project Wizard
Se2ngs snip
HERE
Add your VHDL
Code Here
Add Successful
Compila7on Snip
Here
Add Timing Diagram
Here
2.3 – 16-Bit Register
Add your
Project Wizard
Se2ngs snip
HERE
Add your VHDL
Code Here
Add Successful
Compila7on Snip
Here
Add Timing Diagram
Here
2.4 – Program Counter Register
Add your
Project Wizard
Se2ngs snip
HERE
Add your VHDL
Code Here
Add Successful
Compila7on Snip
Here
Add Timing Diagram
Here
2.5 – 8 Register RAM
Add your
Project Wizard
Se2ngs snip
HERE
Add your VHDL
Code Here
Add Successful
Compila7on Snip
Here
Add Timing Diagram
Here
2.6 – Extra Credit – n Register RAM – RAM64
Add your
Project Wizard
Se2ngs snip
HERE
Add your VHDL
Code Here
Add Successful
Compila7on Snip
Here
Add Timing Diagram
Here
2.7 – Extra Credit – Arithme@c Logic unit -ALU
Add your
Project Wizard
Se2ngs snip
HERE
Add your VHDL
Code Here
Add Successful
Compila7on Snip
Here
Add Timing Diagram
Here
